This invention relates to a bipolar transistor logic circuit and more particularly to an ALSTTL (Advanced Low-power Schottky Transistor - Transistor Logic) output circuit.
FIG. 1 shows a conventional ALSTTL output circuit. In FIG. 1, a first npn type Schottky barrier bipolar transistor 4 receives an input signal at its base. The first transistor 4 becomes conductive when the input signal is a signal designating output of a low level logic signal on an output node 3. The transistor 4 is non-conductive when the input signal is a signal designating output of a high level logic signal on the output node 3. The collector of the first transistor 4 is connected to a first node 1, which may be at 5V, for example, through a first load element 10, which may be a resistor.
An npn type Schottky barrier bipolar transistor 6 and an npn type bipolar transistor 7 are Darlington-connected. The base of the transistor 6 is connected to the collector of the first transistor 4 and the collector of the transistor 6 is connected to the collector of the transistor 7. The emitter of the transistor 6 is connected to the base of the transistor 7. The collector of the transistor 7 is connected to the first potential node 1 through a second load element 8, which may be a resistor.
The base of an npn type Schottky barrier bipolar transistor 5 is connected to the emitter of the first transistor 4 and the collector of the transistor 5 is connected to the output node 3. The emitter of the transistor 5 is connected to a second node 2, which may be ground, for example.
The anode of a Schottky barrier diode (SBD) 9 is connected to the output node 3 and the cathode of the SBD 9 is connected to the collector of the first transistor 4. The SBD 9 discharges charge stored in a charge storage device (such as a capacitor) connected to the output node 3 such that current can flow to the base of the transistor 5 through the transistor 4 when the potential of the output node 3 changes from "high" to "low".
In discussing the operation of the above output circuit, let it be assumed that a low-level input signal is supplied to the base of the first transistor 4. At this time, the first transistor 4 is non-conductive, and so the transistor 5 also is non-conductive. On the other hand, as the potential at the collector of the first transistor 4 is increased through potential applied at the potential node 1, the Darlington-connected transistors 6 and 7 become conductive. Accordingly, current flows to the output node 3 from the first potential node 1 through the second load element 8 and the transistor 7, and the potential of the output node 3 is "high" (V.sub.OH). At this time, the charge storage device connected to the output node 3 stores a charge.
Next, assume the input signal changes to a "high" level from a "low" level. The first transistor 4 then becomes conductive, and the collector current flows, limited by the first load element 10. At this time, a part of the charge stored in the charge storage device flows to the base of the transistor 5 as the part of the above-mentioned collector current through the SBD 9 and the first transistor 4. As a result, current flows to the collector of the transistor 5 in accordance with the current amplification rate of the transistor 5. The charge stored on the output node 3 is discharged rapidly through the transistor 5, and the potential of the output node 3 decreases promptly.
After that, as the transistor 5 becomes conductive and draws out the current from the output node 3, the potential of the output node 3 becomes "low". On the other hand, as the potential at the collector of the first transistor 4 decreases, the abovementioned Darlington-connected transistors 6, 7 become non-conductive.
The first transistor 4 is conductive when the potential of the input signal at its base is higher than the sum of the base-emitter voltage V.sub.BE5 of the transistor 5 and base-emitter voltage V.sub.BE4 of the first transistor 4 based on the potential at the second potential node 2. The first transistor 4 is non-conductive otherwise. The relationship between the potential of the output node 3 and the input signal is shown in FIG. 2.
In the above output circuit, as the charge stored in the charge storage device connected to the output node 3 is rapidly discharged to provide an immediate change to a "low" level when the potential of the output node 3 changes to a "low" level from a "high" level, the output state at the output node 3 changes suddenly when the charge storage device connected to the output node 3 is smaller, as shown in the dotted line of the waveform (b) of FIG. 2.
When the capacitance of the charge storage device is 10pf, the time t.sub.f, when the charge is discharged to 10% from 90% of the original charge, is 2.0 ns. Such an immediate change of the output node 3 causes crosstalk, ringing, or oscillation. As a result, the above described output circuit cannot be provided easily with another circuit such as a printed wiring board, on the same substrate.
The reason for the above-mentioned difficulty is as follows. If it is assumed that this kind of output circuit is combined with a printed circuit board, the capacitance on the output node of output circuit is about 10 pf and the objective value of the above time t.sub.f, which is not influenced by crosstalk, etc., must be more than 2.2 ns. If t.sub.f is smaller than 2.2 ns, it is easy for crosstalk, etc. to occur because of parasitic capacitance or inductance between signal lines on the printed circuit board. Accordingly, the above output circuit, with t.sub.f being 2.0 ns, could not be combined with the printed circuit board.
The kind of output circuit just described is disclosed in MITSUBISHI SEMICONDUCTORS DATABOOK: BIPOLAR DIGITAL IC ALSTTL, 1985, p. 2-90. This output circuit also has a switching transistor connected between the collector of the first transistor 4 and the cathode of the SBD 9 in the output circuit as shown in FIG. 1. This circuit has the same problem as the output circuit shown in FIG. 1.